Frame Synchronizer: Decision Point and Delay Optimization : Technical Support

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Frame Synchronizer: Decision Point and Delay Optimization Print

Modified on: Mon, 9 Feb, 2026 at 10:03 AM

The decision point of the frame synchronizer is located exactly at the start of a frame (zero position). If the reference cable connected to the source and the SDI cable connected to the frame synchronizer are longer than the reference cable connected directly to the frame synchronizer, the video signal arrives late. Depending on the cable length, this delay can already amount to approximately 100 pixels. In such cases, PVDs may introduce a total delay of up to two frames.

Most PVDs provide the InputToRefTolerance parameter, which shifts the decision point by 12 µs toward the back of the frame. At 1.5G or 3G operation, this corresponds to 1,782 pixels, which is roughly half a video line.

To reduce the delay caused by shared reference positioning, it is recommended to enable the InputToRefTolerance parameter.

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Frame Synchronizer: Decision Point and Delay Optimization Print

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